It is known in the art to operate an integrated memory circuit (such as an SRAM) at a plurality of supply voltages. For example, an integrated memory circuit may be supplied with a relatively high supply voltage (for example, 1.26V) in one mode of operation and further supplied with a relatively low supply voltage (for example, 0.6V) in another mode of operation. The static noise margin (SNM) of the SRAM, however, can significantly deteriorate in the relatively low supply voltage mode of operation. To address this problem, read assist (RA) circuits are connected to the SRAM to increase stability. A commonly used read assist circuit is connected to the word line (WL) to effectuate a technique referred to as word line under-drive (WLUD) which improves SNM by reducing pass gate transistor strength. A drawback of this technique is a timing penalty due to reduced read current.
Reference is now made to FIG. 1 showing a block diagram of an integrated memory circuit 10. The circuit 10 includes a memory array 14 formed by a plurality of rows and columns. Each column is defined by a pair of bit lines that are complementary and noted as bit line true BLT and bit line bar BLB, with a memory cell 20 coupled between the pair of bit lines BLT, BLB at each row location and driven by a corresponding word line WL. The word lines WL are driven by a row decoder circuit 26 which operates to decode an address ADD and select, based on the decoded address, one word line WL for actuation. A sense amplifier circuit 30 is coupled to the plurality of pairs of bit lines through a column multiplexing circuit 32. The sense amplifier circuit 30 includes a plurality of sense amplifiers 36. The column multiplexing circuit 32 is controlled by a column decoder circuit 40 to selectively connect bit line pairs to the sense amplifiers 36 of the sense amplifier circuit 30 in response to the decoded address ADD. The configuration and operation of column multiplexed memory circuits is well known to those skilled in the art.
Reference is made to FIG. 2 which shows a schematic diagram of the memory cell 20 implemented as a six transistor (6T) static random access memory (SRAM) cell. The cell 20 includes two cross-coupled CMOS inverters 22 and 24, each inverter including a series connected p-channel and n-channel MOSFET transistor pair. The inputs and outputs of the inverters 22 and 24 are coupled to form a latch circuit having a true data storage node QT and a complement data storage node QB. The cell 20 further includes two transfer (passgate) transistors 26 and 28 whose gate terminals are driven by a wordline (WL). Transistor 26 is source-drain connected between the true data storage node QT and a node associated with a true bitline (BLT). Transistor 28 is source-drain connected between the complement data storage node QB and a node associated with a complement bitline (BLB). The source terminals of the p-channel transistors 40 and 42 in each inverter 22 and 24 are coupled to receive a high supply voltage (for example, Vdd) at a high supply node, while the source terminals of the n-channel transistors 44 and 46 in each inverter 22 and 24 are coupled to receive a low supply voltage (for example, Gnd) at a low supply node. The high supply voltage Vdd at the high supply node and the low supply voltage Gnd at the low supply node comprise the power supply set of voltages for the cell 20. The wordline WL is coupled to the output of row decoder 26 (FIG. 1) and is driven by a wordline driver circuit (not shown) that typically comprises a series connected p-channel and n-channel MOSFET transistor pair forming a logic inverter. The wordline driver circuit is also coupled to receive the high supply voltage (Vdd) at the high supply node and is referenced to the low supply voltage (Gnd) at the low supply node.